Conventional circuits, capable of frequency division by two in the UHF band, are either narrow band, or they require specially shaped waveforms at the input. Additionally, these circuits generally constitute a large number of components and dissipate an excessive amount of power.
Typical circuits capable of frequency division below the UHF band include a pair of transistors arranged to divide-by-two in a configuration referred to as current mode flip-flop with emitter triggering. With this arrangement, the bases and collectors of a pair of transistors are cross-coupled first by a pair of capacitors and second through resistors connected to the collectors. As the frequency increases, however, the propagation delay from transistor base to collector becomes significant resulting in an inability of the transistors to follow the input and to divide-by-two.
A circuit for achieving a relatively high frequency divide-by-two action is disclosed in U.S. Pat. No. 3,536,933, entitled "High Speed Divide-By-Two Dual Transistor Circuit", by D. E. Sanders, one of the inventors of the present invention. The circuit disclosed in the aforementioned patent employs a wideband transformer as the collector load of a pair of cross-coupled transistors which are emitter triggered with the input wave to be divided. The wideband transformer enables each transistor to regenerate without waiting for the propagation delay of the other transistor. Although the aforementioned circuit performs well it does not lend itself to efficient miniaturization due to the use of the wideband transformer. In addition higher frequency signals, for example, signals in the 400 to 500 MHz band are not handled efficiently.
The present inventive circuit lends itself readily to miniaturization, operates with higher frequency signals, and uses less power than the prior art circuits.